Current ROM bit cell tiling for arbitrary codes is done by tiling basic code0 cells and/or code1 cells. FIGS. 1A and 1B show design schematics of code0 and code1 bit cells, respectively. As shown in FIG. 1A, a code0 cell is typically implemented as a single MOSFET having its gate tied to a word line (WL) and its drain connected to a coding node. The bit line (BL) of the code0 node is set to a floating voltage representing a logic zero. A code1 cell also includes a MOSFET having its source coupled to VSS and its gate tied to a WL as shown in FIG. 1B. The drain of the MOSFET in the code1 cell is coupled to a BL, such that when the MOSFET is turned on, VSS is coupled to the BL. The turning on and off of the MOSFETs illustrated in FIGS. 1A and 1B are controlled by the WLs, which provide logic ones or zeroes to the gates of the MOSFETs.
The tiling of code0 and code1 cells described above is compatible with masked ROM cells with isolated oxide definition (OD) islands for each bit cell. FIG. 2A illustrates one example of layout of bit cells using the masked ROM with isolated OD islands. However, these conventional layouts suffer from long OD (LOD) effect, polysilicon (poly) spacing effect (PSE), and OD spacing effect (OSE), all of which cause device degradation. FIG. 2B is a graph of NMOS ldsat versus surface area (μm) for the bit cell layout illustrated in FIG. 2A. As shown in FIG. 2B, the smaller the surface area of the bit cell layout, the greater the degradation as seen by the sharp roll-off region at the left of the graph. FIG. 2C is a graph of NMOS Dldsat versus spacing (μm) for the bit cell layout illustrated in FIG. 2A. As shown in FIG. 2C, the device degradation increases as the spacing between OD islands increases in a lengthwise direction in the layout illustrated in FIG. 2A.
Accordingly, a improved method for laying out a ROM is desirable.